1. Field of the Invention
The present invention relates to a data transfer control system, a direct memory access (DMA) controller, and a DMA data transfer method. More particularly, the present invention relates to a data transfer control system, a DMA controller, and a DMA data transfer method that can change the way of data transfers.
2. Description of the Related Art
There are computer systems that need to process a large amount of data objects while inputting and outputting them at very high speeds. To achieve the purpose, those systems often employ a special data transfer mechanism, other than the main processor for general data processing. This mechanism is known as a direct memory access (DMA) controller. The DMA controller, or DMAC, normally works independently of the main processor to transfer data between different memory areas according to specified source and destination addresses and data size.
The DMAC transfers data while the main processor is engaged in other data processing tasks. It is an advantage of using a DMAC that the main processor is free from the overhead of data transfers. Some DMA architectures include a dedicated memory for a DMAC, so that the DMAC can make access to its dedicated memory without causing contention with main memory access by the main processor. See, for example, Japanese Patent Application Publication No. 7-244632 (1995). This technique provides the main processor with an increased data processing efficiency.
Data objects that a DMAC is supposed to transfer may vary depending on the requirement of each system application. Some systems only require simple memory-to-memory transfers. Others may need to transfer more complex data objects such as data in rectangular areas, or require a sophisticated transfer sequence according to some prescribed rules. Also, the memory addresses are not necessarily fixed, but determined through calculations.
Conventional DMACs have I/O registers for receiving DMA parameters including source address, destination address, and data size. A host processor sets those parameters in the DMAC and then gives a start command to let the specified DMA transfer begin. Such DMACs are implemented as peripheral hardware circuits with fixed functions for use as an independent component or as an integral part of the system chip set. Since the functionality of conventional DMACs is mostly hard-wired, different circuit designs are required for different system applications. For example, some DMACs have a plurality of DMA channels to support parallel data transfers. Other DMACs contain a FIFO buffer to store a queue of DMA requests. Actually, a variety of application-specific DMACs are used in different computer systems.
DMACs with hardware-oriented design, however, are limited in terms of functional flexibility. Some of their functions may be superfluous in a certain class of applications, while they may fail to provide necessary features in other applications. Think of, for example, a system with a four-channel DMAC. While this four-channel design satisfies the system's requirements initially, it is possible that there arises later a need for an application which really uses, say, six DMA channels. Since only four DMA channels are available, and since that number is physically fixed in this case, system engineers have to manage to configure the application with the limited DMA resources. The penalty is an increased processing overhead, which is likely to result in a performance degradation.
Most DMACs are implemented as supplementary circuits that help the main processor in doing tasks. Cost requirements and power consumption requirements of a system impose a limit on DMAC designs. For these reasons, DMACs are only allowed to have relatively simple addressing capabilities, and it is therefore difficult for ordinary DMACs to realize DMA transfers with sophisticated addressing patterns. Some existing DMACs support special addressing, but most of them are designed for particular applications and often inappropriate for other applications.
As described above, existing hardware-implemented DMACs are so simple and limited in their flexibility that they are unable to provide the data transfer patterns required in actual applications. That is, conventional DMACs are designed primarily for use in simple applications. In the case where complex data transfers are required, the main processor executes them with its own data transfer instructions while calculating source and destination addresses. This method, however, consumes much of the computation time of the main processor, thus leading to degradation of system performance.
In view of the above, several researchers have proposed a multi-processor system to make a complex data transfer possible. See, for example, Japanese Patent Application Publication No. 7-13920 (1995). According to this approach, the system employs another microprocessor (sub-processor) other than its main processor. Instead of having a dedicated hardware circuit, the system uses this sub-processor as a DMAC. If its performance is sufficiently high in an intended application, the sub-processor can perform a sophisticated data transfer by generating memory addresses on the fly with its own arithmetic functions. This programmable sub-processor also brings flexibility to DMA functions.
It should be noted that the sub-processor described above is a general-purpose processor. A data transfer using a general-purpose processor takes more steps in calculating memory addresses than a hard-wired DMAC does. More specifically, the sub-processor executes load and store instructions back to back in order to emulate a memory-to-memory data transfer. This means that the source data is once read into a register in the processor and then written in the destination memory. In contrast, a typical hard-wired DMAC can transfer a burst of data directly between memories at a high speed, concentrating on memory address generation and read/write control. Although the sub-processor approach offers higher flexibility, it has an obvious disadvantage in transfer speeds. The cost is another problem of this approach, because a general-purpose processor requires a greater amount of circuit resources than an ordinary single-purpose DMAC does.
According to the multi-processor system disclosed in the second patent literature, all the main processor data, DMA parameters, and sub-processor programs are placed together in a single memory space. The proposed system uses a dual-port random access memory (DPRAM) for this purpose, which accepts simultaneous access from the main processor and sub-processor. The problem is, however, that the sub-processor has to fetch instructions as well as to read and write data through the same port of the DPRAM, thus slowing down the execution speed.
The primary purpose of using a DMAC is to execute data transfers transparently to the main processor's computation (i.e., to parallelize the two processes, ideally with no time wasted). If the sub-processor was slow, a consequent delay of DMA data transfers would hamper the main processor from proceeding to the next task. The speed of DMA transfers is therefore important for the performance of the system.